#wire_load_model or mode
set_app_var auto_wire_load_selection false
#set_wire_load_model  -name ZeroWireload
set_wire_load_mode top

#set_max_leakage_power 0 
set_max_area 0
set_max_fanout 64 [current_design]
set_max_capacitance 10 [current_design]
#set_max_transition 0.8 [current_design]
set_max_transition 0.6 [current_design]

create_clock -period 20.000 -name clk [get_ports clk]
#set_clock_uncertainty -setup 1.000 [get_clocks clk]

#create_generated_clock -name clk_driver -divide_by 2 -source clk [get_ports clk]
#create_generated_clock -name clk_driver -divide_by 1 -source clk [get_ports clk]
#create_generated_clock -name clk_driver_1 -divide_by 1 -source clk [get_ports clk]
#create_generated_clock -name clk_driver_2 -divide_by 1 -source clk [get_ports clk]
#create_generated_clock -name clk_driver_3 -divide_by 1 -source clk [get_ports clk]
#create_generated_clock -name clk_inv -divide_by 1 -source clk [get_ports clk]
#group_path 
#set ports_clock_root [filter_collection [get_attribute [get_clocks] sources] object_class==port]
#group_path -name reg2out -from [all_registers -clock_pins] -to [all_outputs] 
#group_path -name in2reg -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_registers -data_pins]
#group_path -name in2out -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_outputs]
#group_path -name reg2reg -from [all_registers] -to [all_registers]

set_ideal_network -no_propagate [get_ports clk]
set_ideal_network -no_propagate [get_ports rstn]
